1. Field of the Invention
The present invention relates to a data processing apparatus comprising a precharged circuit, and in particular to techniques for providing a conditional-invert function for a precharged circuit of a data processing apparatus.
2. Description of the Prior Art
Circuits employing precharged circuits have a precharge phase, in which the input(s) and output(s) of each precharged circuit are generally driven to a predetermined logic value. When designing data processing apparatus having one or more precharged circuits, it is well-known that significant attention needs to be paid to the inputs to each precharged circuit, since these inputs must only transition from the predetermined logic value to the other logic value when the precharged circuit is enabled, i.e. when the precharged circuit is not in its precharge phase.
For example, if the precharged circuit is based on n-type logic, then it is usual for the input(s) and output(s) of the precharged circuit to be driven to a logic "0" value during the precharge phase. Clearly, in this instance, if logic on one of the input lines were to cause that input to transition from logic "0" to logic "1" during the precharge phase, then this will adversely affect the precharging of the precharged circuit, in that the precharged circuit may not be in the intended state when the precharge phase is exited. Indeed, such a change at the input may cause the output of the precharged circuit to also transition from a logic "0" to a logic "1" value.
This problem becomes particularly acute when a number of such precharged circuits are connected in series to form domino logic. When precharging such domino logic, all of the precharged circuits are preferably precharged at the same time such that the output of each precharged circuit is driven to the same logic value, e.g. a logic "0" value for n-type precharged circuits. Clearly, if one of the inputs to a precharged circuit transitions during the precharge phase, the effect of this is likely to ripple through all of the precharged circuits forming the domino logic, the result of this being that the domino logic is unlikely to be in the intended state when the precharge phase is exited, and so is unlikely to operate in the correct manner on entering the active phase in which the precharged circuits are enabled.
This problem is discussed on page 309 of the publication entitled "Principles of CMOS VLSI Design" by Weste and Estraghian, Second Edition, published by Addison Wesley, where it is stated that, due to the above mentioned problems, it is important to ensure that only non-inverting logic is included within the domino logic. This makes such precharged circuitry incompatible with exclusive-OR (XOR) functions, which can be either inverting or non-inverting, and hence would introduce uncertainty into the state achieved as a result of the precharge phase of any precharged circuit receiving at one of its inputs the output of such an XOR function.
Despite the above limitations, it is often preferable to use precharged circuits, since they are typically significantly faster than non-precharged circuits. Hence, in principle, it is preferable to use precharged circuits to form circuitry such as fast adders, such as are used in the Arithmetic Logic Unit (ALU) of a microprocessor. However, such an ALU will often include a conditional-invert function on one of the inputs to the adder logic, in order to implement "subtract" functions as well as "add" functions.
Given the requirement for a conditional-invert function within a typical ALU, then one prior art approach has been to use a non-precharged adder circuit instead of a precharged adder circuit, despite the reduction in speed that results from the use of a non-precharged adder circuit. Such an arrangement is illustrated in FIG. 1. As illustrated in FIG. 1, the non-precharged adder circuit 100 has two inputs (A and B). One input value, Bdata, is provided over line 110 to input B, whilst a second data value, Adata, is passed over line 125 to the input of an XOR gate 130. The other input of the XOR gate 130 receives an invert A (InvA) signal over path 120. If InvA has a logic "0" value, then Adata is output from the XOR gate 130 over line 105 to input A of the adder circuit 100. However, if InvA has a logic "1" value, then the value of Adata is inverted by the XOR gate 130, and the inverted value is provided over line 105 to input A. The non-precharged adder circuit 100 then performs an "add" function based on the signals received at inputs A and B, and the result is output from the output terminal S over line 115.
Whilst the circuit illustrated in FIG. 1 enables addition and subtraction to be performed, it is a relatively slow circuit, since a non-precharged adder circuit 100 is used. However, if the non-precharged adder circuit is to be replaced by a precharged adder circuit in order to increase speed, then it is essential that certain steps are put in place to ensure that the circuitry operates correctly, despite the presence of the XOR gate 130. A known prior art technique is illustrated in FIG. 2. In FIG. 2, the non-precharged adder circuit 100 is replaced by a precharged adder circuit 200. However, to ensure that the precharged adder circuit 200 is precharged correctly, and that in particular the presence of the XOR gate 130 does not affect the precharged state of the adder circuit 200, it is necessary to provide some self-timed logic 220 to introduce a delay prior to the precharged adder circuit 200 being enabled over path 230. By introducing this delay, it is ensured that the precharged adder circuit 200 remains in its precharge phase until the XOR logic 130 has settled.
Whilst the approach in FIG. 2 can ensure correct operation of the precharged adder circuit 200, it is difficult to implement such a self-timed path reliably, and this problem is compounded if the XOR logic is preceded by another functional unit, such as a barrel shifter. Further, the provision of self-timed logic 220 increases the size of the overall adder circuitry, and also the presence of such a delay impacts on the potential speed advantage to be gained from using the precharged adder 200 rather than the non-precharged adder 100.
It is hence an object of the present invention to provide an improved technique for enabling conditional-invert functions to be employed in association with precharged circuits.